A phase-locked loop (“PLL”) is a feed-back control system that generates an output signal whose phase is related to the phase of the input reference signal. A conventional or analog PLL includes a charge-pump based phase and frequency detector (“PFD”), a passive component based loop filter (e.g., resistors and capacitors), a voltage controlled-oscillator (“VCO”) and a frequency divider. Typically, all of these devices, except the frequency divider, are implemented by analog methods.
Analog design approaches become more and more problematic as the physical size of circuits are reduced due to new integrated circuit (“IC”) processing techniques. However, all digital phase locked loops (“ADPLLs”) have shown great advantages in design and implementation methods for PLLs in deep submicron IC processing. Additionally, ADPLLs yield better testability, programmability, stability, and portability than traditional analog PLLs. As a result, the adoption of ADPLLs is a new trend in frequency synthesizers and clock generator designs.
Generally, there are two types of ADPLLs. One type of ADPLLs is based on a time-to-digital converter (“TDC”) locking method and the other is based on a bang-bang (“B-B”) locking method. The TDC based ADPLLs have relatively high performance and can be analyzed by a linear model. A drawback of the TDC based ADPLLs is that it is very hard to design a TDC which has fine resolution, wide measuring range, and good linearity. The B-B based ADPLLs eliminate the use of a TDC and have relatively simple structure. However, it is not without drawbacks since B-B based ADPLLs cannot be analyzed by a linear model and are not suitable for fractional-N PLL architectures.
Therefore, it is desirable to provide new methods and apparatuses for ADPLLs, which can combine a TDC locking method and a B-B locking method, while having the flexibility to vary the parameters for the resolution and the measuring range of the ADPLL.